Busy, busy, busy
It’s been busy here. I’ve just sent a set of board files off to Hackvana for manufacture. Among them are boards for two new projects here, an iPod Nano gen6 Display Breakout board and an iPhone 4/4S HSMC board. Both of these projects will utilize VHDL that I will be designing to drive a MIPI display. Initial target will be the Altera Cyclone V, but I hope to make it generic enough to also work with the Cyclone IV and Lattice MachXO2 devices.
Another FPGA project on the go has me working with high speed ADCs and interfacing with National (now TI) ChannelLink LVDS receivers. The latter will be a blog post, but I’d like to get the LVDS HSMC breakout board back and built before I go into more detail. A picture is worth a thousand words, and being able to demonstrate something that works will make for a much better blog post.
Outside of the FPGA side of things, I have been taking a closer look at the Cypress PSoC 5LP devices for a client project. I was a little let down when I discovered that the programmable logic in them more closely resembles a CPLD rather than an FPGA but reading more about their UDB design it seems like they’ve struck an okay balance between the simplicity of a CPLD structure and the flexibility of an FPGA LAB/ALM/CLB. Having a standard ARM in there certainly helps keep things simpler from a software standpoint since I can just use the regular old GCC toolchain that I know and love. The downside is the Windows-only design software for the analog and digital stuff. I haven’t gotten far enough into things to know if I can write VHDL to create digital logic or not.
One last thing... I stumbled upon the Intermediate Electronics Blog by Julio Rodriguez. I am not one for videos because I find I can’t stay focused on them but Julio has some interesting content and his approach where he takes only one or two narrow subjects and talks about them is nice. I’ll be keeping an eye on his video blog.