Digital Clocking

From this alteraforums post.

Many threads on this forum involve clocks that are not driven directly by device pins or PLLs. This thread addresses design considerations for clocks driven by registers or combinational logic.

The main focus of this forum thread is how to avoid problems with ripple and gated clocks that can make timing closure difficult or result in failures in actual hardware even when the reported timing seems good.

For related information about ripple and gated clocks, see the document written by someone else at That document has many examples of clock circuits like various kinds of clock dividers and clock muxes with instructions for using TimeQuest to constrain them.

The Quartus II Design Assistant has some design-rule checks for ripple and gated clocks. This forum thread does not cover all considerations related to the Design Assistant rules. For more information, see the Quartus II on-line help page for each rule. Run the Design Assistant by itself using “Processing –> Start –> Start Design Assistant.” Run it during compilation by enabling it at “Assignments –> Settings –> Design Assistant (category on left side) –> Run Design Assistant during compilation (checkbox).”

Terminology used in this forum thread:

In Quartus II terminology, “ripple clock” means any clock driven by a register. A common case is a clock divider.

In Quartus II terminology, “gated clock” can mean any clock driven by an unregistered logic function, usually by a LUT or ALUT in the FPGA logic array blocks. Gated clocks can provide an on/off gating function. The term also applies to clocks driven by other combinational logic functions like clock multiplexers. This thread discusses on/off gating and clock multiplexing in particular, but the information applies to any clock path containing combinational logic.

In this thread, “derived clock” means either a ripple clock or gated clock. It is essentially any clock that is not driven directly by a device pin or PLL.

In this thread, “global routing” refers to device-wide global clock networks, regional clock networks, dual-regional clock networks, and fast regional clock networks.

Design guidelines for ripple and gated clocks:

These guidelines are the recommended choices listed in order from most to least preferred.
1. Do not use ripple or gated clocks; use clock enables or PLLs instead.
2. Have no synchronous data paths going to or from the derived clock domain.
3. If you have synchronous data paths going to or from the derived clock domain, then add clock uncertainty.
4. If you have hold violations going to or from the derived clock domain, then set “Optimize Hold Timing” to ”All Paths”.
5. If you have setup or hold violations going to or from a derived clock domain using global routing, then try nonglobal routing.

Each of these guidelines is covered in a separate post.

Design guidelines 1 and 2 prevent the negative consequences of clock skew resulting from ripple and gated clocks. Design guidelines 3, 4, and 5 reduce but do not necessarily eliminate the negative consequences of the clock skew. The clock skew considerations covered in the post for design guideline 3 also apply to designs using design guidelines 4 or 5.

Gated clocks can have timing hazards such as glitches. Design guidelines to avoid timing hazards in gated clocks like clock muxes are covered in a separate post.


Using Clock Control Blocks

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